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MX9691A
SINGLE CHIP SOLID STATE DISK CONTROLLER
FEATURES
Host Interface * Fully compatible with PCMCIA Release 2.1, and PC Card ATA Release 1.02 specification. * Compatible with all PC Card Services and Socket Service. * Fast ATA host-to-buffer burst transfer rates up to 20MB/ sec. which support PIO mode 4(16.6MB/sec) and DMA mode 3(16.6MB/sec). * Automatic sensing of PCMCIA or ATA host interface. * Integrated PCMCIA attribute memory of 256 bytes (CIS). - CIS and Buffer RAM use same SRAM area to simplify internal bus design * PCMCIA card configuration register support. * Polarity control for host reset signal. * PCMCIA twin card support. * PCMCIA based ATA address decode support. * Emulate the IBM task file for PC/AT. * Separate status for Bus reset and Host program reset. * Separate Host and Disk interrupt pins. Flash Memory Interface * Support all the control signals to execute read/write/ erase operation for flash memory. * Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit flash memory or 64MB(unformatted) capacity for 16 pcs. 32Mbit flash memory. * Flash Memory Power Down or write protect control support. - Don't power down the flash memory chip which used to store firmware * Flash Memory Ready/Busy status detect. * Inverted data bus control to reduce program operation in DOS FAT and ECC code field. * Optional store firmware in flash memory array w/o externalROM. - Shadow ROM control to allow code fetch during data program or erase * Media speed is upto 8MB/sec, sustain read data rate and 125KB/sec write data rate. Buffer RAM control * Dual port circular Buffer RAM control * 1KB data Buffer RAM. * Automatically correct error data in Buffer RAM. - Single word error correct and double word detect. * Provide logic to speed up Buffer RAM access. * Support 8 bit as well as 16 bit transfer on host bus. DSP core * High performance MX93011 DSP (21Mips) core. * 4KB Internal RAM(direct access). * 2KB Internal expansion RAM(indirect access) for store data or shadow ROM space. * ICE debugging mode supported to ease system verification. * Lower power and automatic power saving operation Technology * 128 pin LQFP * 0.6um Low-power, High-speed CMOS technology. * 5V10% or 3.3V5% Utility Support * * * * Upload firmware from Host. Physical Devices test. Preformat. CIS Manufacturer code and Model code edit.
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PIN CONFIGURATION
INPACK#
HRESET
HCE1#
HCE2#
IREQ#
HWE#
HOE#
HD11
HD12
HD13
HD14
HD15
IOW#
HA10
WAIT 98
IOR#
GND
GND
VCC
VCC
HD3
HD4
HD5
HD6
HD7
HA9
HA8
HA7
HA6
HA5
HA4 99
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
97
HA3
FA16 FA15 A14 A13 A12 LED# GND A11 A10 A9 A8 FA19 FRY/FBY# INT1# NMI# HOLD# VCC WRFLASH0# WRFLASH1# FA18 FA17 A15 A7 A6 GND A5 A4 A3 A2 A1 A0 PWD0#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
HA2 REG# HA1 SPKR HA0 GND STSCHG HD0 HD8 HD1 HD9 HD2 HD10 IOIS16# PWR_RST TEST VCC X1 X2 GND ROMWR# ROMCS# XF# HLDA# VCC X32I X32O GND DCE# PCE# WR# RD#
MX9691A
GND
RDFLASH0#
VCC
GND
VCC
RDFLASH1#
FCE7#
FCE2#
FCE1#
FCE0#
FCE6#
FCE5#
FCE4#
FCE3#
GND
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
D10
D11
D12
D13
D14
D15
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MX9691A
GENERAL DESCRIPTION
The Macronix's Solid State Disk controller is fully integrated flash memory controller that provides all the control logic for a PC Card ATA flash memory. The MX9691A combines 1KB dual-port buffer and buffer manager, integrated MX93011 DSP core , and a complete host interface for both the PC Card ATA and ATA standard. The MX9691A is typically configured with up to 32MB(unformatted) capacity for 16 pcs. 16Mbit flash memory or 64MB(unformatted) capacity for 16 pcs. 32Mbit flash memory. The MX9691A supports all the control signals to execute read/write/erase operation for flash memory chip. The MX9691A is fully compliant with the PC Card ATA specification. It includes 256 bytes of integrated attribute memory(for the required Card Information Structure) and four Card Configuration registers. The PCMCIA device driver can access the MX9691A ATA command block through four different modes by writing the different modes by writing the configuration index of the attribute memory configuration option register.
PIN DESCRIPTION
Host Interface Symbol HA[10:0] No. Type 92,94, 96-97, I 99,101-103, 106,109,113 84-89,116-117, I/O 121-128 104,111 107,110 100 I I I Description Host address line 10-0. These pins include internal pull-up resistors. Host data line 15-0. These pins include internal bus holder circuit that keep previous state when tri-state. Host memory read/write/mode select : Both pins include internal pullup resistors that is default in PCMCIA mode. Host I/O access. Both pins include internal pull-up resistors. The host reset signal, when active, initializes the control/status registers and stops any command in process.In PCMCIA mode, the signal is active high. In ATA extension mode, this signal is active low. This signal include internal pull-down resistor. WAIT or INPUT CHANNEL READY : In both PCMCIA and ATA extension modes, this signal holds host transfers until the controller is ready to respond. READY/BUSY or HOST INTERRUPT : In PCMCIA mode, this signal has two functions. In PCMCIA common memory mode, this signal is ready/busy. It is asserted busy by the reset logic, and can be deasserted by the local uC. In PCMCIA I/O mode, this signal is IREQ#. In ATA extension mode, this active high signal is HOSTINT, which, when enable, send an interrupt to the host.
HD[15:0]
HOE#,HWE# IOR#,IOW# HRESET/ HRESET#
WAIT/ IOCHRDY RDY/BSY#/ IREQ#/ HOSTINT
98
O,OD
119
O,Z
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Symbol WP/IOCS16# No. 83 Type O,OD Description WRITE PROTECT or 16-bit I/O TRANSFER : In PCMCIA mode, this bit has two functions. In PCMCIA common-memory mode,this signal indicates write protect. In PCMCIA I/O mode, when IOIS16# is as serted low, it indicates that a 16-bit data transfer is active on PCMCIA bus. In ATA extension mode, the IOCS16# signal indicates that a 16-bit buffer transfer is active on the host bus. This open drain signal is only driven on assertion(low). Attribute memory and I/O select : In PCMCIA mode, this signal is used to select attribute memory and I/O space. In ATA extension mode, this signal is used during DMA with the DREQ, IOR# and IOW# signals to transfer data between the host and the MX9691A. This pin includes an internal pull-up resistor. Card enable 1 or Chip select 0: In PCMCIA mode,this signal is card enable 1. This signal can enable either even or odd numbered-address bytes onto HD7:0. In ATA extension mode, this signal accesses the MX9691A command block registers. This input is ignored during DMA data transfer, i.e. when the DACK# signal is low. This pin includes an internal pull-up resistor. Card enable 2 or Chip select 1: In PCMCIA mode,this signal is card enable 2. This signal can enable odd numbered-address bytes onto HD15:8. In ATA extension mode, this signal accesses the MX9691A control block registers. This pin includes an internal pull-up resistor. Input Acknowledge or DMA request : In PCMCIA mode, this signal is asserted when the MX9691A is configured to respond to I/O card read cycles at all addresses. In ATA extension mode, this signal is DREQ and is issued during DMA transfers to indicate that the MX9691A is ready for DMA transfer. Speaker or slave present : In PCMCIA mode, the output-enable for this signal is controlled by the card configuration registers. In ATA extension mode, this signal is used as the slave-present detector. Status change or pass diagnostics : In PCMCIA mode, this signal is used to indicate changes in the RDY/BSY#,WP signals in card con figuration registers. In ATA extension mode, this active low signal is used between two embedded ATA drive to indicate that the drive in slave mode has passed diagnostics.
REG#/DACK# 95
I
HCE1#/ CS1FX#
115
I
HCE2#/ CS3FX#
114
I
INPACK#/ DREQ
118
O
SPKR/DASP# 93
I/O
STSCHG/ PDIAG#
90
I/O
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Microcontroller interface : Symbol D[15:0] No. 33-37, 39-41, 55-58, 60-63 3-5, 8-11, 22-24, 26-31 Type I/O Description DSP IO/RAM/ROM/FLASH memory array external data bus. These pins in clude internal pull-up resistors.
A[15:0]
I/O
PCE#
67
I/O
DCE#
68
I/O
RD#
65
I/O
WR#
66
I/O
NMI# INT1#
15 14
I I/O
In normal mode, these signals are output that used as DSP IO/RAM/ ROM external address. A14-A0 are for flash memory array address also. In upgrade mode, these address is used for ROM address that controlled by CYH,CYL registers. In ICE debugging mode, these ad dress are input,asserted by external MX93011 DSP. The internal DSP is disabled. These pins include internal pull-up resistors. In normal mode, this signal is output that is used as external program chip enable. In upgrade mode, this signal is drived to high. In ICE de bugging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal mode, this signal is output that is used as external data chip enable. In upgrade mode, this signal is drived to high. In ICE debug ging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal mode, this signal is output that is used as DSP IO/RAM/ ROM external read. In upgrade mode, this signal is output and as serted when the data register is read in host interface. In ICE debug ging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal mode, this signal is output that is used as DSP IO/RAM/ ROM external write. In upgrade mode, this signal is drived to high. In ICE debugging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder cir cuit. Non maskable interrupt pin. This pin includes an pull-up resistor. In normal mode, this signal is input that is used as interrupt pin. Interrupt will be internally asserted also when data transfer done, or command end. In ICE debugging mode, this signal is output and as serted when data transfer done, or command end. This pin includes an pull-up resistor.
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Symbol HOLD# No. 16 Type I/O Description In normal mode, this signal is input that is used as holding DSP clock down and release bus. Bus hold will be internally asserted also when upgrade mode enable. In ICE debugging mode, this signal is output and asserted when upgrade mode enable. In ICE debugging mode, this signal is output and asserted when upgrade mode enable. This pin includes an pull-up resistor. In normal mode, this signal is output that is used as ack to HOLD# signal. This signal will be internally sent to PCMCIA/ATA interface also when upgrade mode enable. In ICE debugging mode, this signal is input and ack to HOLD# when upgrade mode enable. This pin in cludes an pull-up resistor. External flag, this pin can be directly written by one DSP instruction. Default inactive (logic high). In ICE debugging mode, this signal is used to reset CPU.
HLDA#
73
I/O
XF#/CPURST# 74
O
Flash Memory Interface : Symbol FA19/CLE No. 12 Type O Description In random mode, this signal is used as flash memory chip high address line 19. In sequential mode, this signal is used as flash memory chip command latch enable. In random mode, this signal is used as flash memory chip high address line 18. In sequential mode, this signal is used as flash memory chip address latch enable. This signal is used to select whether the MX9691A initializes in normal mode or in ICE debugging mode at poweron reset. If this pin go high, then the MX9691A will switch to normal mode at power-on reset,and if this pin remains low, then the MX9691 A will initializes in ICE debugging mode. This pin includes an internal pull-up resistor. ICEMODE ICE debugging mode select : ICEMODE=1 --> Normal mode ICEMODE=0 --> ICE debugging mode
FA18/ALE/
20
I/O
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Symbol FA17/EROM No. 21 Type I/O Description This signal is used as flash memory chip high address line 17. This signal is used to select whether the firmware store in flash memory array or in separate external ROM at power-on reset. If this pin go high, then the firmware will be executed in flash memory array, and if this pin remains low, then the firmware will be executed in separate external ROM. Store firmware in external ROM or Flash memory array: EROM = 0 --> Store in External ROM EROM = 1 --> Store in flash memory array This pin includes an internal pull-up resistor. This signal is used as flash memory chip high address line 16-15. These signals are used to select configuration in ATA extension mode at poweron reset. ATADET1 is connected to DSP's IPT1. ATADET0 is connected to DSP's IPT0. VDD is connected to IPT2. Master/Slave selection in ATA mode : ATADET1 ATADET0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives This power-on configuration can be accessed from PCMCIA/ATA port 601Ch bit3-2. These pins include internal pull-up resistors. Flash memory ouptut enable 1 for bank1: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8 = 1(i.e. FA23=1). Note: Flash memory access window is mapped to 32KW data and code space 8000h~ffffh. Flash memory ouptut enable 0 for bank0: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8 = 0(i.e. FA23=0). Flash memory write enable 1 for bank1: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601Fh bit 8 = 1(i.e. FA23=1). Flash memory write enable 0 for bank0: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601Fh bit 8 = 0(i.e. FA23=0).
FA[16:15]/ ATADET[1:0]
1-2
I/O
RDFLASH1#
54
O
RDFLASH0#
42
O
WRFLASH1#
19
O
WRFLASH0#
18
O
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Symbol FCE[7:0]# No. 43-44,46-47, 49-52 Type O Description Flash memory chip enable 7-0 : In random mode, These signals are decoded from port 601Dh bit 7-5 when flash memory read or port 601Fh bit 7-5 when flash memory write. Decoding combination : bit7 bit6 bit5 FCE[7:0]# 000 11111110 001 11111011 010 11101111 011 10111111 100 11111101 101 11110111 110 11011111 111 01111111 In sequential mode, These are decoded from port 601Dh bit 7-5 only when port 601Eh bit 2 is set. Deep power down output 0 for bank0: This signal will put the flash memory chips of bank0 in deep power-down mode. PWD0# is active low;PWD0# high enables normal operation. PWD0# also locks out erase or program operation when active low providing data protection during power transitions. Power down pin PWD0# will be active if FA23=1. Deep power down output 1 for bank1: This signal will put the flash memory chips of bank1 in deep power-down mode. PWD1# is active low;PWD1# high enables normal operation. PWD1# also locks out erase or program operation when active low providing data protection during power transitions. Power down pin PWD1# will be active if FA23=0. Flash memory Ready/busy input: This signal indicate the state of erase or program operation in flash memory chips.This pin includes an internal pull-up resistor.
PWD0#
32
O
PWD1#
64
O
FRY/FBY#
13
I
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Control ROM interface : Symbol ROMCS#/ FWIN# No. 75 Type O Description ROM chip select/Flash memory data buffer enable : In normal mode, this signal is used as ROM chip enable if firmware that stored in external ROM. In ICE debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array. ROM write enable/Flash memory data buffer direction control: In normal mode, this signal is used as ROM write enable if firmware that stored in external ROM. In ICE debugging mode, this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array.
ROMWR#/ FDIR
76
O
Miscellaneous : Symbol X1 X2 X32I X32O TEST No. 79 78 71 70 81 Type I O I I I Description Crystal input. Crystal ouput. 32K Crystal input. 32K Crystal output. This signal is used to select the main system clock, either from external clock source if this signal is high or from internal PLL circuit if this signal is low. This pin includes an internal pull-up resistor. Power on reset, CMOS Schmite-triggered: The MX9691A include debouncing circuit to stabilize internal DSP reset signal. LED output: This signal is connected to external LED in debugging system to indicate system status. The LED will be turn-on during reset. The contorl firmware will turn off the LED after H/W initialization and pass diagnostics. If system fail, the control firmware will flash the LED to indicate some error occur. This signal will be high if port 601Ch bit0 set to 1 or OPTR bit2 set to 1. 5 volt or 3.3 volt Power pin Ground pin
PWR_RST# LED#
82 6
I O
VCC GND
17,45,53,72, 80,105,112 7,25,38,48, 59,69,77,91, 108,120
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Functional and Operation Description
Block Diagram
Clock
External Memory Bus
Clock & Reset
MX93011 DSP CORE
4KB Internal RAM 2KB Internal RAM
Register Bank
Host Interface PCMCIA/ATA
PCMCIA/ATA interface
1KB Buffer RAM
Flash Memory Control
Flash Interface
256 Byte CIS RAM
Buffer RAM Control
ECC Control Logic
MX9691A Signal Chip Solid State Disk Controller
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Power-on detection: (1). Store firmware in external ROM or Flash memory array : FA17/EROM = 0 --> Store in External ROM FA17/EROM = 1 --> Store in flash memory array (2). Master/Slave selection in ATA extension mode : FA16/ATADET1 FA15/ATADET0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives (3). ICE debugging mode select : FA18/ICEMDOE = 0 --> ICE debugging mode FA18/ICEMODE = 1 --> Normal mode (4). Flash memory data buffer control ROMCS# is replaced by FWIN# if ICE debugging mode & firmware in flash memory array ROMWR# is replaced by FDIR if ICE debugging mode&firmware in flash memory array (5). PCMCIA or ATA extension select HOE# HWE# mode 0 0 ATA extension mode others PCMCIA mode
System Memory Map : (1). Data Space : Address 0000h~007fh 0080h~07ffh 0800h~5fffh 6000h~63ffh 6400h~6fffh 7000h~73ffh 7400h~77ffh 7800h~7fffh 8000h~ffffh
Function & Usage Internal RAM (128W) to store control variables Internal RAM(1920W) for flash memory algorithm usage User define (22kW) I/O range(1kW): ATA CTL. use I/O range (6000h~601fh) User define (3kW) User define (1kW) Internal RAM (1kW) for expansion RAM or shadow ROM space ROM Data space(2kW) Flash memory access windows(32kW)
(2). Program Space : Address 0000h~77ffh 7800h~7fffh 8000h~ffffh
Function & Usage ROM program space (32kW) Unused Flash memory access windows(32kW)
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Registers definition: (1). Register List : Type of Register PCMCIA/ATA Interface PC INTERRUPT CONTROL BUFFER MANAGER AND DMA ECC Control Flash Memory Interface
Location 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600Bh, 6010h, 6011h, 6012h, 6013h, 6019h, 601Ah, 601Bh, 601Ch 6009h, 600Ah 6008h, 6014h, 6015h, 6016h, 6017h, 6018h 600Ch, 600Dh, 600Eh, 600Fh 601Dh, 601Eh, 601Fh
(2). Register Description : Port 6000h : Bit
Function Description AT CONTROL/STATUS REGISTER Default reset value : 01h R/W: DRIVE READY (drive 0) R/W: DRIVE SEEK COMPLETE (drive 0) R/W: CORRECTED DATA R: ATA INT. ENABLE R: AT SOFTWARE RESET R/W: HOST INTERRUPT R/W: ERROR BIT R/W: BUSY BIT
7 6 5 4 3 2 1 0
Port 6001h : Bit 7:0
Function Description Default reset value : 00h R/W: ERROR REGISTER (map to command block 1f1h)
Port 6002h : Bit 7:0
Function Description Default reset value : 01h R/W: SECTOR COUNT REGISTER (map to command block 1f2h)
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Port 6003h : Bit 7:0 Function Description Default reset value : 01h R/W: SECTOR NUMBER REGISTER (map to command block 1f3h)
Port 6004h : Bit 7:0
Function Description Default reset value : 00h R/W: CYCLINDER LOW REGISTER (map to command block 1f4h)
Port 6005h : Bit 7:0
Function Description Default reset value : 00h R/W: CYCLINDER HIGH REGISTER (map to command block 1f5h)
Port 6006h : Bit 7:0
Function Description Default reset value : A0h R/W: DRIVE/HEAD REGISTER (map to command block 1f6h)
Port 6007h : Bit 7:0
Function Description Default reset value : 00h R: COMMAND REGISTER (map to command block 1f7h)
Port 6008h : Bit
Function Description BUFFER RAM SIZE CONTROL REGISTER Default reset value : 40h R/W: TEST MODE 1 for HAP/DAP test 0 : DISABLE 1 : ENABLE R/W: BIT WRITE GATE STATE OF DRIVE 0 : ENABLE 1 : DISABLE
7
6
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Bit 5 Function Description R: PCMCIA/ATA 0 : ATA extension mode 1 : PCMCIA mode R/W: Auto DAP increment 0 : Disable 1 : Enable R/W: Shadow ROM control 0 : Disable 1 : Enable R/W: BUFFER RAM SIZE CONTROL 00x : 32KW 010 : 16KW 011 : 8KW 100 : 4KW 101 : 2KW 110 : 1KW 111 : 512W
4
3
2:0
Port 6009h : Bit
7 6 5 4 3 2 1 0
Function Description HOST INTERRUPT STATUS Default reset value : 00h R: Power-Down timer time-out detected R: Card configuration register write detected R: CIS accessed detected R: Hreset detected R: PC SRST(or PCMCIA SRST) DETECTED R: PC STATUS READ DETECTED R: PC SELECTION R: PC TRANSFER DONE
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Port 600Ah : Bit Function Description HOST INTERRUPT ENABLE Default reset value : 00h R/W: Power-Down timer time-out detected enable. R/W: Card configuration register write detected enable R/W: CIS accessed detected enable R/W: Hreset detected enable R/W: PC SRST(PCMCIA SRST) DETECTED ENABLE R/W: PC STATUS READ DETECTED ENABLE R/W: PC SELECTION ENABLE R/W: PC TRANSFER DONE ENABLE
7 6 5 4 3 2 1 0
Port 600Bh : Bit 7:0
Function Description Default reset value : 00h R: Feature register (map to command block 1f1h)
Port 600Ch : Bit
7
6
Function Description ECC CONTROL REGISTER Default reset value : 00h R/W: ECC FUNCTION SUSPEND 0 : NORMAL 1 : SUSPEND R/W: CORRECTION SPEED SELECT 0 : FULL SPEED 1 : HALF SPEED R/W: ENCODE/DECODE FUNCTION SELECTION 0 : ENCODE 1 : DECODE R/W: RESET ECC CIRCUIT 0 : RESET 1 : NORMAL R: UNCORRECTABLE ERROR FLAG R: CORRECTABLE ERROR FLAG R: CORRECTION DONE FLAG R/W: START ECC CORRECT FUNCTION ENABLE/DISABLE 0 : DISABLE 1 : ENABLE
5
4
3 2 1 0
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Port 600Dh : Bit 15:0 Function Description Default reset value : 0000h R/W : ECC 0 REGISTER
Port 600Eh : Bit 15:0
Function Description Default reset value : 0000h R/W : ECC 1 REGISTER
Port 600Fh : Bit 15:0
Function Description Default reset value : 0000h R/W : ECC 2 REGISTER
Port 6010h : Bit 7:0
Function Description Default reset value : 00h R: Configuration Option register (map to attribute memory 200h)
Port 6011h : Bit 7:0
Function Description Default reset value : 00h R: Card Configuration and status register (map to attribute memory 202h)
Port 6012h : Bit 7:0
Function Description Default reset value : 0Ch R: Pin replacement register (map to attribute memory 204h)
Port 6013h : Bit 7:0
Function Description Default reset value : 00h R: Socket and copy register (map to attribute memory 206h)
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Port 6014h : Bit 15:0 Function Description Default reset value : 0000h R/W : HOST ADDRESS POINTER
Port 6015h : Bit 15:0
Function Description Default reset value : 00ffh R/W : AT STOP POINTER
Port 6016h : Bit 15:0
Function Description Default reset value : 0000h R/W : DISK ADDRESS POINTER
Port 6017h : Bit
7 6 5
4
Function Description DMA CONTROL REGISTER Default reset value : 08h R/W: DRIVE READY (drive 1) R/W: DRIVE SEEK COMPLETE (drive 1) R/W: set BSY upon XFER done 0 : DISABLE 1 : ENABLE R/W: ENABLE AUTO INTERRUPTS - AT ONLY 0 : DISABLE 1 : ENABLE R/W: BUFFER RAM CHIP ENABLE 0 : ENABLE 1 : DISABLE R/W: HOST BUS DIRECTION 0 : START BUFFER -> AT BUS 1 : START AT BUS -> BUFFER WHEN SET R: A COMPLETION OF AT DMA XFER R/W: START DATA TRANSFER BETWEEN AT BUS AND BUFFER RAM 0 : DISABLE 1 : ENABLE
3
2
1 0
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Port 6018h : Bit 15:0 Function Description R/W : ACCESS PORT INTO BUFFER RAM
Port 6019h : Bit 7 6 5 4 3 2
1 0
Function Description PCMCIA control register R: ATA extension mode R: Common memory mode R: I/O mode R/W: host ready R/W: no drive address R/W: Internal registers write pulse width 0 : 2 system clock 1 : 1 system clock R/W: Force ATA mode R/W: Force PCMCIA mode
Port 601Ah : Bit
7 6
5 4 3
Function Description Auxi_ctl_1 reg. Default reset value : 00h R/W : DASP R/W : Host Interrupt level mode or pulse mode select 0: Level mode 1: Pulse mode R/W : PDIAG R/W : DASP output enable R/W: write protect enable 0: Disable 1: Enable R/W: PDIAG output enable R/W: master/slave mode enable 0: Disable 1: Enable R/W: master/salve of ATA mode 0: master 1: slave
2 1
0
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Port 601Bh : Bit Function Description Auxi_ctl_2 reg. Default reset value : 00h Reserved. R/W: Force the CPU that fetch codes from flash memory array R/W: Force the system that become ICE debugging mode R/W: Host interface RESET polarity 0: Low active 1: High active R/W: Disk interrupt polarity 0: Low active 1: High active
7:4 3 2 1
0
Port 601Ch : Bit
Function Description Auxi_ctl_3 reg. Default reset value : 0000h Reserved R/W : Test mode 2 for timer 0 : Normal mode 1 : Test mode enable R : DRQ R : Time out status 1 : Time out event occurence R/W: Timer enable/disable 0 : Disable 1 : Enable
15 14
13 12 11
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Port 601Ch : Bit 10:9 Function Description R/W: Power-down timer time-out select for 25MHz main clock 00 : 16 x 1.28 = 20.48 sec. 01 : 8 x 1.28 = 10.24 sec. 10 : 4 x 1.28 = 5.12 sec. 11 : 2 x 1.28 = 2.56 sec. R : ICE debugging mode detected 0 : ICE debugging mode 1 : Normal R/W : Inverted data bus for access flash memory. 0 : Inverted 1 : Non-inverted R: External ROM detect. 0: Firmware stored in external ROM 1: Firmware stored in flash memory array R/W: Shadow ROM space control 00 : 512 bytes, Range: 7400h ~ 74ffh 01 : 1Kbytes, Range: 7400h ~ 75ffh 10 : 1.5Kbytes, Range: 7400h ~ 76ffh 11 : 2Kbytes, Range: 7400h ~ 77ffh R : Master/Slave mode detect in ATA mode 00 : Master of two drives 10 : Slave of two drives 11 : One drive R/W: PIO/DMA mode select 0: PIO mode 1: DMA mode R/W: LED output
8
7
6
5:4
3:2
1
0
Port 601Dh : Bit 9:0
Function Description Default reset value : 0000h R/W : Flash memory Read address FA[24:15] latch for random mode When data space 8000h ~ ffffh is read, the output of the flash memory read address latch will be used.
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For sequential mode this register has different definitions 9:8 Reserved 7:5 R/W: FCE select for sequential mode 000: FCE0 001: FCE2 010: FCE4 011: FCE6 100: FCE1 101: FCE3 110: FCE5 111: FCE7 4 R/W: Command latch enable (FA19/CLE) 0 : Disable 1 : Enable 3 R/W: Address latch enable (FA18/ALE) 0 : Disable 1 : Enable 2:0 Reserved
Port 601Eh : Bit
Function Description Flash memory control register Default reset value : 08Ah R/W: Flash memory deep power down control 0 0 : Enable Power Down pin PWD0# active or FA23=1 for 16Mbit Random access flash memory 1 : Disable R : Ready / Busy status 0 : BUSY 1 : READY R/W: Flash memory type select 00 : 4M flash memory /Bank 0 select for sequential select 01 : 16M flash memory /Bank 1 select for sequential select 10 : Reserved 11 : Reserved
7
6
5:4
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Bit 3 Function Description R/W: Flash memory deep power down control 1 0 : Enable Power Down pin PWD1# active or FA23=0 for 16Mbit Random access flash memory 1 : Disable R/W: CE# enable for sequential mode 0 : Disable 1 : Enable R/W: Sequential mode select 0 : Random mode 1 : Sequential mode R/W: Flash memory write pulse width control 0 : 1 system clock 1 : 2 system clock
2
1
0
Port 601Fh : Bit
Function Description Default reset value : 0000h R/W : Flash memory Write address FA[24:15] latch for random mode When data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash memory write address latch will be used. For sequential mode this register is reserved.
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ELECTRICAL SPECIFICATIONS
DC Characteristics 1 : Ta = 0oC to 70 oC, VCC = 5V10% Symbol VCC VIL1 VIH1 VIL2 VIH2 VOL VOH ICC1 ICC2 ICC3 ICC4 IL CIN COUT Parameter Power Supply voltage Input Low voltage (TTL) Input High voltage (TTL) Input Low voltage (CMOS) Input High voltage (CMOS) Output Low voltage Output High voltage Supply Current 1 Supply Current 2 Supply Currect 3 Supply Current 4 Input Leakage Input Capacitance Output Capacitance Min 4.5 2.0 0.8 3.5 0.4 2.4 40 35 10 1 10 14 16 Max 5.5 0.8 Units V V V V V V V mA mA mA mA uA pf pf Conditions VCC=5V VCC=5V VCC=5V VCC=5V IOL=8mA IOH=-8mA f = 25Mhz, Active mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC f = 25Mhz, Idle mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC f = 25Mhz, Standby mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC f = 0Mhz, Sleep mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC 0< VIN < VCC VIN=0V VOUT=0V
Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods less than 20ns.
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DC Characteristics 2 : Ta = 0 oC to 70 oC, VCC = 3.3V5% Symbol VCC VIL1 VIH1 VIL2 VIH2 VOL VOH ICC1 Parameter Power Supply voltage Input Low voltage(TTL) Input High voltage(TTL) Input Low voltage(CMOS) Input High voltage(CMOS) Output Low voltage Output High voltage Supply Current 1 Min 3.1 2.0 0.8 2.7 0.4 2.2 20 Max 3.5 0.8 Units V V V V V V V mA Conditions VCC=3.3V VCC=3.3V VCC=3.3V VCC=3.3V IOL=4mA IOH=-4mA f = 16Mhz, Active mode, CL = 0pf, VCC=3.5Volt,Temperature= 0oC f = 16Mhz, Idle mode, CL = 0pf, VCC=3.5Volt,Temperature= 0oC f = 16Mhz, Standby mode, CL = 0pf, VCC=3.5Volt,Temperature= 0oC f = 0Mhz, Sleep mode, CL = 0pf, VCC=3.5Volt,Temperature= 0oC 0< VIN < VCC VIN=0V VOUT=0V
ICC2 ICC3
Supply Current 2 Supply Currect 3
15 5
mA mA
ICC4 IL CIN COUT
Supply Current 4 Input Leakage Input Capacitance Output Capacitance
0.5 10 14 16
mA uA pf pf
Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods less than 20ns.
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MX9691A
AC Characteristics (Condition : Ta=0 oC to 70 oC, VCC = 5V10% or VCC = 3.3V5%)
DSP Interface Timing VCC = 5V10% Symbol Description Tw In ICE mode, WR# pulse duration when the data are accessed by external DSP. Trd In ICE mode, RD# to output delay when the data are accessed by external DSP. Tcs Chip select access cycle Taa Address access cycle Trds Data setup time before RD# high Tdh Data hold time after RD# high
Min. 4Tc
Typ.
Max.
Unit
34 1.5Tc 1.5Tc 12 0 4.5Tc 4.5Tc
ns ns ns ns ns
VCC = 3.3V5% Symbol Description Tw In ICE mode, WR# pulse duration when the data are accessed by external DSP. Trd In ICE mode, RD# to output delay when the data are accessed by external DSP. Tcs Chip select access cycle Taa Address access cycle Trds Data setup time before RD# high Tdh Data hold time after RD# high
Min. 4Tc
Typ.
Max.
Unit
34 1.5Tc 1.5Tc 15 0 4.5Tc 4.5Tc
ns ns ns ns ns
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A[15:0] DCE#
WR#
Tw
HD[15:0]
A[15:0] DCE#
RD#
Trd
D[15:0]
DCE#/PCE#
Tcs Taa
A[15:0]
RD#
D[15:0]
Trds
Tdh
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Power Reset Timing VCC = 5V10% or VCC = 3.3V5% Symbol Description Tw(rst) Reset low pulse width
Min. 3Tc
Typ.
Max.
Unit ns
Clock Timing VCC = 5V10% Symbol Description Tc(c) Clock cycle time Tlpd(c) Clock low pulse duration(Tc=40ns) Thpd(c) Clock high pulse duration(Tc=40ns)
Min. 40 16 16
Typ.
Max. 24 24
Unit ns ns ns
VCC = 3.3V5% Symbol Description Tc(c) Clock cycle time Tlpd(c) Clock low pulse duration(Tc=62.5ns) Thpd(c) Clock high pulse duration(Tc=62.5ns)
Min. 62.5 25 25
Typ.
Max. 37.5 37.5
Unit ns ns ns
CLK IN Thp PWR RST# Tc Tw(rst) Tlpd
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Interrupt Timing VCC = 5V10% Symbol Description Tw INT1# low pulse duration Tf INT1# fall time
Min. 1.5Tc
Typ.
Max. 10
Unit ns ns
VCC = 3.3V5% Symbol Description Tw INT1# low pulse duration Tf INT1# fall time
Min. 1.5Tc
Typ.
Max.
Unit ns ns
HOLD# Timing VCC = 5V10% or VCC = 3.3V5% Symbol Td(al-h) Td(hh-ha) Ten(ah-a) Description HLDA# low to address tri-state HOLD# high to HLDA# high Address driven after HLDA# high Min. 0 0 0.5Tc -10 Typ. 0.5Tc 0.5Tc Max. 0.5Tc+10 Tc Unit ns ns ns
INT1
Tf Tw
HOLD# HLDA# Td(al-h) AD[15:0]
Td(hh-ha)
Ten(ah-a)
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PCMCIA Bus Timing 1: Common Memory and Attribute memory Access Timing VCC = 5V10% Symbol Parameter T1 Chip enable setup time before output enable T2 Output data enable time from HOE# T3 Chip disable hold time following output disable T4 Output data disable time following HOE# T5 Chip enable setup time before HWE# T6 Chip disable hold time following write disable T7 Data setup time before HWE# T8 Data hold time following HWE#
Min (ns) 0 1.5
Max (ns) 31 10.5
0 2 0 2.5
VCC = 3.3V5% Symbol Parameter T1 Chip enable setup time before output enable T2 Output data enable time from HOE# T3 Chip disable hold time following output disable T4 Output data disable time following HOE# T5 Chip enable setup time before HWE# T6 Chip disable hold time following write disable T7 Data setup time before HWE# T8 Data hold time following HWE#
Min (ns) 0 3
Max (ns) 47 17
0 2.5 0 3
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Common Memory and Attribute Memory Read Timing
HA[10:0] REG# CE[2:1]# T1 HOE# T3 T2 T4 HD[15:0]
Common Memory and Attribute Memory WriteTiming
HA[10:0] REG# CE[2:1]# T5 HWE# T8 HD[15:0] T6
T7
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PCMCIA Bus Timing 2: I/O mode Access Timing VCC = 5V10% Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Parameter Address hold time following IOR# REG# setup time before IOR# REG# hold time following IOR# CE# setup time before IOR# CE# hold time following IOR# Address setup time before IOR# INPACK delay from IOR# falling INPACK delay from IOR# rising IOIS16 falling delay after Address changed Data delay after IOR# falling IOIS16 rising delay after Address changed Data hold time following IOR# Address hold time following IOW# REG# setup time before IOW# REG# hold time following IOW# CE# setup time before IOW# CE# hold time following IOW# Address setup time before IOW# IOIS16 rising delay after Address changed IOIS16 falling delay after Address changed Data setup time before IOW# Data hold time following IOW#
Min (ns) 2 0 0 0 2 0
Max (ns)
10 10.5 14 32 12.5 20 3 0 0 0 2 0 10.5 14 0 2.5
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VCC = 3.3V5% Symbol Parameter T1 Address hold time following IOR# T2 REG# setup time before IOR# T3 REG# hold time following IOR# T4 CE# setup time before IOR# T5 CE# hold time following IOR# T6 Address setup time before IOR# T7 INPACK delay from IOR# falling T8 INPACK delay from IOR# rising T9 IOIS16 falling delay after Address changed T10 Data delay after IOR# falling T11 IOIS16 rising delay after Address changed T12 Data hold time following IOR# T13 Address hold time following IOW# T14 REG# setup time before IOW# T15 REG# hold time following IOW# T16 CE# setup time before IOW# T17 CE# hold time following IOW# T18 Address setup time before IOW# T19 IOIS16 rising delay after Address changed T20 IOIS16 falling delay after Address changed T21 Data setup time before IOW# T22 Data hold time following IOW# Min (ns) 2 0 0 0 2 0 Max (ns)
18 18 23.5 47 20 31 4 0 0 0 2.5 0 20 23.5 0 3
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ID Read Timing
HA[10:0] T1 REG# T2 T4 CE[2:1]# IOR# T6 INPACK# IOIS16# T9 HD[15:0] T10 T11 T7 T8 T5 T3
T12
I/O Write Timing
HA[10:0] T13 REG# T14 T16 CE[2:1]# IOW# T18 T19 IOIS16# T20 HD[15:0] T17 T15
T21
T22
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Flash Memory Interface Timing VCC = 5V10% Symbol Tw(a-ce) Twas Tw(wrflash) Tr(a-ce) Tr(rd-0e)
Parameter FCE# fall time after DSP address decode when write FCE# setup time before WRFLASH# falling edge WRFLASH# low pulse duration FCE# fall time after DSP address decode when read RDFLASH# fall time after RD# falling edge
Min. 5.5 10 1Tc* 5.5 4.5
Max. 15 30 15 11.5
Unit ns ns ns ns ns
VCC = 3.3V5% Symbol Tw(a-ce) Twas Tw(wrflash) Tr(a-ce) Tr(rd-0e)
Parameter FCE# fall time after DSP address decode when write FCE# setup time before WRFLASH# falling edge WRFLASH# low pulse duration FCE# fall time after DSP address decode when read RDFLASH# fall time after RD# falling edge
Min. 8 15 1Tc* 8 7
Max. 24.5 50 25 20
Unit ns ns ns ns ns
* Note:These timing are only for 1-system clock of flash memory write pulse is employed (601E[0]=0). If 2-system clock of pulse width is selected (601E[0]=1), the minimum of Tw(wrflash) is 2Tc.
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Flash memory write timing
A[15:0] Tw(a-ce) FCE[7:0] WR# Twas Tw(wrflash) WRFLASH#
Flash memory Read timing
A[15:0] Tr(a-ce) FCE[7:0] RD# Tras
RDFLASH#
Latchup Characteristics Min. -2.0V -2.0V -100mA Max. 12.0V VCC+2.0V +100mA
Input Voltage with respect to GND on all VCC pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except GND. Test conditions : VCC=5.0V, one pin at a time.
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MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
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TEL:+65-348-8385 FAX:+65-348-8096
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MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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